The largest takeaway is that TSMC is pursuing a novel packaging tech called Chip-on-Panel-on-Substrate (CoPoS), aimed at reducing costs while boosting performance for future AI processors.

Packaging strategy is becoming a fierce competitive battleground in semiconductors as AI models demand more memory, compute, and bandwidth.

CoPoS shifts from wafer-based to panel-level processing, enabling larger package sizes and improved material utilization for complex AI accelerators.

Mass production of CoPoS is slated for the second half of 2028, with glass serving only as a temporary carrier during manufacturing, not in the final package.

CoPoS is designed to complement, not replace, TSMC’s CoWoS, and could win early traction with NVIDIA’s forthcoming Feynman AI chips due to the need for larger, high-bandwidth AI packages.

The broader trend is that advanced packaging innovation, alongside transistor shrinking, is increasingly critical for boosting AI chip performance and cutting overall production costs.

If CoPoS succeeds, it could enable bigger, more capable AI processors at lower costs, signaling a shift in how performance gains are achieved in modern chips.