Alibaba and China Telecom Launch AI-Driven Data Center in Shaoguan, Boosting Domestic Chip Infrastructure
April 8, 2026
Alibaba and China Telecom announce a new data center in Shaoguan, Guangdong, powered by Alibaba’s Zhenwu AI chips, signaling a major push to accelerate domestic AI infrastructure.
The facility will deploy 10,000 Zhenwu chips designed for AI training and inference, with scalable plans to reach 100,000 chips to support large parameter models.
This data center highlights a seamless integration of Alibaba’s custom AI silicon with telecommunications infrastructure to boost performance, efficiency, and scalability for AI workloads.
Officials envision the data center serving multiple sectors, from healthcare to advanced materials, signaling broad commercial applications beyond cloud services.
A technology committee led by Alibaba’s CEO and composed of top AI and tech leaders has been formed to accelerate Alibaba’s AI development.
The project sits within China’s broader push for semiconductor self-sufficiency amid U.S. restrictions on chip access, and is framed as part of a shift toward domestic AI hardware and data-center growth.
Analysts note a contrast with U.S. AI investments, with Chinese firms prioritizing revenue-driven deployments using domestic hardware to reduce foreign chip dependency.
The initiative reflects intensified competition in global AI infrastructure as major Chinese players expand domestic AI semiconductor capabilities.
Alibaba’s broader strategy encompasses in-house chip design via its T-head unit, data-center expansion, and AI models for sale through its cloud division, underscoring cloud as a fast-growing business.
The move aligns with broader momentum in domestic AI hardware, alongside Huawei’s Ascend-based compute clusters recently coming online.
coverage across industry voices emphasizes AI model safety, vulnerability mitigation, and cybersecurity defenses as central themes in deploying powerful AI systems.
The data center is expected to initially operate with 10,000 Zhenwu chips and support models with hundreds of billions of parameters, with future scaling to tens of thousands of chips.
Summary based on 2 sources
