Navitas unveils its 5th-generation GeneSiC technology platform, introducing a 1200 V SiC MOSFET line built on a Trench-Assisted Planar (TAP) architecture that blends planar gate ruggedness with trench-region benefits.

The new 5th-generation TAP platform complements Navitas’ existing 2300 V and 3300 V devices from the 4th-generation family, with additional products expected to be announced in the coming months.

The design achieves roughly a 25% improvement in the QGD/QGS ratio and maintains a stable threshold voltage (VGS(th) ≥ 3 V) to help prevent parasitic turn-on in high-noise environments.

Navitas projects an extrapolated gate-oxide failure time exceeding one million years at 18 V VGS and 175°C, signaling high reliability for demanding applications.

The company is qualifying the parts to an AEC-Plus grade, surpassing standard AEC-Q101 and JEDEC requirements with extended high-temperature, high-voltage stress tests and fast dynamic switching assessments for mission-critical use.

Paul Wheeler, VP and GM of Navitas’ SiC business unit, emphasizes driving performance and reliability to meet AI data-center and energy-infrastructure deployment needs.

The TAP platform delivers about a 35% improvement in the RDS(on) x QGD metric over the previous 1200 V devices, enabling lower switching losses and higher switching frequencies.

Navitas has published a white paper detailing the TAP architecture on its website, offering technical background on the technology.