Samsung’s HBM4E stacks use a 1c DRAM node at 10-nanometer-class, paired with a 4-nm logic die from its own foundry, aiming for better production stability, higher yields, and readiness for mass production.

By combining 1c DRAM, 4nm base dies, and advanced packaging, Samsung is pursuing high-throughput, thermally stable AI memory solutions to lead both production readiness and technology.

Manufacturing relies on a sixth-generation 10-nm-class 1c DRAM process with a 4-nm logic base die to balance performance and heat dissipation for data-center deployments.

The roadmap envisions future 32GB (8-layer) and 64GB (16-layer) variants, signaling scale-up potential beyond the initial 48GB (12-layer) configuration.

Samsung is targeting NVIDIA, AMD, and Google for shipments, signaling an early-mover edge in AI memory and heightening competitive pressure on SK Hynix and Micron.

Mass production will align with customer demand and schedules, indicating a ramp-up aligned to buyer adoption.

Industry context points to a looming $1 trillion data center memory spend by 2027, underscoring the strategic importance of next-generation memory architectures for large language models and multimodal AI workloads.

The 12-layer HBM4E delivers per-pin speeds of 14–16 Gbps and up to 3.6 terabytes per second of bandwidth per stack.

HBM4E packages contain 48 GB per stack, with plans for 32GB eight-layer and 64GB sixteen-layer variants based on demand.

HBM4E achieves 48 GB per stack by integrating Samsung’s 1c 10nm-class DRAM with a 4nm logic base die, enabling higher capacity and bandwidth.

Competition is expected to intensify as SK hynix reportedly prepares to send customer samples of its own HBM4E, potentially accelerating timelines if development stays on track.

Samsung has begun shipping samples of its 12-layer HBM4E memory, marking the industry’s first shipments of this generation as of late May 2026.